Broad Impact of Electrostatic discharge (ESD) on Product Quality and Reliability (Part 2 of 2)
In this seminar, we discuss the challenges designers will be facing over the next several years. Changes in technology will continue to put pressure on designers to provide adequate protection but often without good information or tools. Highlights of the following will be covered: The shrinking design window for CMOS integrated circuits; changes in component level ESD threshold targets and the lack of availability of component information; the implications of new packaging and interconnect technologies such as through silicon vias (TSV); design of system connection and user interfaces; the use and misuse of component level ESD information for system level protection and emerging methods for co-design; and the evolution of EOS/ESD testing methods and standards.
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